1. Field of the Invention.
The invention relates to the field of metal-oxide-semiconductors (MOS), electrically programmable read-only memory (EPROM) cells employing floating gates.
2. Prior Art.
Read-only memories (ROMs) are often used, particularly in the computer industry, for storing programs, constants and the like. Frequently, for development purposes and also when limited numbers are required, electrically programmable read-only memories (EPROMs) are employed EPROMs permit the user to insert data into memory, rather than having the memory manufacturer insert the data during fabrication of the memory. One class of these memories is fabricated with MOS technology and employs cells (with floating gates) which are erased by exposing the memory to radiation such as ultraviolet light. Commercial versions of these memories are sold under Part Nos. 2708 and 2716, in addition to other numbers.
The initial erasable EPROM memories with floating gate cells employed p-channel devices which were charged through avalanche injection such as the device described in U.S. Pat. No. 3,660,819. In order to charge a floating gate in this device, a relatively high programming voltage is needed to avalanche a junction and provide a source of high energy electrons which are injected onto the floating gate.
As the prior art went to denser and faster structures, n-channel MOS EPROM cells were employed rather than p-channel. One such device is shown in U.S. Pat. No. 3,996,657. In addition to the reversal of the conductivity types of the various regions, these n-channel devices commonly employ two gates, the usual floating gate and an additional gate located above the floating gate, used as a control gate. This control gate is used to charge the floating gate and for device selection. Charge is normally injected into the floating gate from the channel region, rather than from the source or drain region as in the case of the previously described p-channel floating gate devices. This is sometimes referred to as channel injection as opposed to the earlier avalanche injection. Improved versions of this n-channel floating gate memory device are described in U.S. Pat. Nos. 4,142,926 and 4,114,255.
Typically, these prior art n-channel EPROM cells require 25 volts for programming. This is a somewhat higher voltage than is normally available for integrated circuit use. Thus, there is some inconvenience associated with programming these devices because of this higher programming voltage. Moreover, it is more difficult to handle these higher voltages in the memory.
As will be seen, the present invention provides a floating gate device somewhat similar to that of the prior art, however, with the distinct advantage of being programmable with a voltage of approximately 12 volts. This is a substantial improvement since 12 volt power supplies are commonly available for integrated circuit use. Also this lower voltage can be decoded more readily on a memory chip.